preliminary rev. 0.3 12/05 copyright ? 2005 by silicon laboratories si532 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si532 d ual f requency xo (10 mh z to 1.4 gh z ) features applications description the si532 dual frequency xo utilizes silicon laboratories advanced dspll ? circuitry to provide a very low jitter clock for all output frequencies. the si532 is available with any-rate output frequency from 10 to 945 mhz and selected frequencies to 1400 mhz. unlike traditional xos where a different crystal is required for each output frequency, the si532 uses one fixed crystal frequency to provide a wide range of output frequencies. this ic based approach allows the crystal resonator to be optimized for superior frequency, stability, and reliability. in addition, dspll clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments often found in communication systems. the si532 ic based xo is factory configurable for a wide variety of user specifications including frequency, supply voltage, and output format. specific configurations are factory programmed into the si532 at the time of shipment, thereby eliminating the long lead times associated with custom oscillators. functional block diagram available with any-rate output frequencies from 10 to 945 mhz and selected frequencies to 1.4 ghz two selectable output frequencies industry standard 7x5 mm package available cmos, lvpecl, lvds & cml outputs 3.3, 2.5, and 1.8 v supply options 3x better frequency stability than saw based oscillators 3rd generation dspll ? with superior jitter performance internal fixed crystal frequency ensures high reliability and low aging lead-free/rohs-compliant sonet/sdh xdsl 10 gbe lan/wan low jitter clock generation optical modules test and measurement fixed frequency xo any-rate 10?1400 mhz dspll? clock synthesis v dd clk+ clk? gnd fs oe ordering information: see page 7. si5602 p reliminary d ata s heet
si532 2 preliminary rev. 0.3 1. electrical specifications table 1. si532 electrical specifications parameter min typ max units notes frequency nominal frequency lvds/cml/lvpecl cmos 10 10 ? ? 945 160 mhz specified at time of order by p/n. also available in bands from 970 to 1134 mhz and 1213 to 1417 mhz. initial accuracy ?1.5 ? 1.5 ppm measured at +25 c at time of ship- ping temperature stability ?20 ?50 ? ? +20 +50 ppm selectable option by p/n. see section 4. "ordering information" on page 7. aging ? ? 10 ppm frequency drift over projected 15 year life outputs symmetry 45 ? 55 % lvpecl: v dd ? 1.3 v (differential) lvds: 1.25 v (differential) cmos: v dd /2 rms jitter for f out > 500 mhz 12 khz to 20 mhz 50 khz to 80 mhz ? ? 0.27 0.30 ? ? ps f out > 500 mhz differential modes: lvpecl/lvds/cml rms jitter for f out of 125 to 500 mhz 12 khz to 20 mhz ?0.5?ps 125 < f out < 500 mhz differential modes: lvpecl/lvds/cml period jitter for f out < 160 mhz peak-to-peak rms ? ? 5 1 ? ? ps any output n = 1000 cycles lvpecl output option mid-level swing (diff) swing (single-ended) v dd ? 1.42 1.1 0.50 ? ? ? v dd ? 1.25 1.9 0.93 v v pp v pp 50 ? to v dd ? 2.0 v lvds output option mid-level swing (diff) 1.125 0.32 1.2 0.40 1.275 0.50 v v pp r term = 100 ? (differential) cml output option mid-level swing ? 0.70 v dd ? 0.75 0.95 ? 1.20 v v pp rterm = 100 ? (differential)
si532 preliminary rev. 0.3 3 cmos output option v oh v ol 0.8xv dd ? ? ? v dd 0.4 vc l =15pf rise/fall time ? ? ? 1 350 ? ps ns cml/lvpecl/lvds at 20% / 80% cmos with cl = 15 pf inputs voltage (v dd ) 3.3 v option 2.5 v option 1.8 v option 2.97 2.25 1.71 3.3 2.5 1.8 3.63 2.75 1.89 v optional parameter specified by p/n current output enabled tristate mode ? ? 90 60 ? ? ma frequency select (fs) v ih v il 0.75 x v dd 0 ? ? v dd 0.5 v fs = ?0? selects f0 fs = ?1? selects f1 output enable v ih v il 0.75 x v dd ? ? ? v dd 0.5 v table 2. absolute maximum ratings parameter symbol rating units supply voltage v dd ?0.5 to +3.8 v storage temperature t s ?55 to +125 c table 1. si532 electrical specifications (continued) parameter min typ max units notes
si532 4 preliminary rev. 0.3 table 3. environmental conditions parameter conditions/test method operating temperature ?40 to +85 c mechanical shock mil-std-883f, method 2002.3 b mechanical vibration mil-std-883f, method 2007.3 a solderability mil-std-883f, method 203.8 gross & fine leak mil-std-883f, method 1014.7 resistance to solvents mil-std-883f, method 2016 table 4. pinout pin symbol function 1 fs frequency select 2 oe output enable 3 gnd ground 4 clk+ oscillator output 5 clk? (n/a for cmos) complementary output (n/c for cmos) 6v dd power suppy voltage
si532 preliminary rev. 0.3 5 2. outline diagram and suggested pad layout figure 1 illustrates the package details for the si532. table 5 lists the valu es for the dimensions shown in the illustration. figure 1. si532 outline diagram table 5. package diagram dimensions (mm) dimension min nom max a 1.45 1.65 1.85 b1.21.41.6 c0.60 typ. d 7.00 bsc. d1 6.10 6.2 6.30 e 2.54 bsc. e 5.00 bsc. e1 4.30 4.40 4.50 l 1.07 1.27 1.47 s 1.815 bsc. r 0.7 ref. aaa ? ? 0.15 bbb ? ? 0.15 ccc ? ? 0.10 ddd ? ? 0.10
si532 6 preliminary rev. 0.3 3. 6-pin pcb land pattern figure 2 illustrates the 6-pin pcb land pa ttern for the si532. table 6 lists t he values for the dimensions shown in the illustration. figure 2. si530 pcb land pattern table 6. pcb land pattern dimensions (mm) dimension min max d2 5.08 ref e 2.54 bsc e2 4.15 ref gd 0.84 ? ge 2.00 ? vd 8.20 ref ve 7.30 ref x1.70 typ y2.15 ref zd ? 6.78 ze ? 6.30 notes: 1. dimensioning and tolerancing per the ansi y14.5m-1994 specification. 2. land pattern design based on ipc-7351 guidelines. 3. all dimensions shown are at ma ximum material condition (mmc). 4. controlling dimension is in millimeters (mm).
si532 preliminary rev. 0.3 7 4. ordering information the si532 was designed to support a variety of options in cluding frequency, tuning sl ope, output format, and v dd . specific device configurations are programmed into the si532 at time of ship ment. a unique part number associated with these options and frequ encies will be assigned. the si532 xo series is supplied in an industry- standard, 7x5 mm package. part numbers for the si532 dual frequency xo ar e determined by following conf iguration tables. silicon labs provides a web browser-based part number configuration to ol to simplify this process. refer to www.silabs.com/ vcxo to access this tool and fo r further ordering instructions. figure 3. part number convention 532 x x 1 st option code v output format a 3.3 lvpecl b 3.3 lvds c 3.3 cmos d 3.3 cml e 2.5 lvpecl f 2.5 lvds g 2.5 cmos h 2.5 cml j 1.8 cmos k 1.8 cml note : cmos available to 160 mhz. b g r tape & reel packaging operating temp range (c) g -40 to +85c part revision letter 532 xo product family 2 nd option code temp stability (ppm, max, ) a 50 b 20 dd frequency designator code two unique frequencies can be specified within the following bands of frequencies: 10 to 945 mhz 970 to 1134 mhz 1213 to 1417 mhz a six digit code will be assigned by silabs for the specified combination of frequencies. note : six digit codes > 000100 refer to dual xos programmed with the lower frequency value selected when fs = 0, and the higher value when fs = 1; six digit codes < 000100 refer to dual xos programmed with the higher frequency value selected when fs = 0, and the lower value when fs = 1. x x x x x x
si532 8 preliminary rev. 0.3 d ocument c hange l ist revision 0.2 to revision 0.3 updated the ?fea tures? section. updated table 1, ?si532 electrical specifications,? on page 2. updated lvds, cml, and cmos electric specifications. updated figure 1, ?si532 outline diagram,? on page 5. updated 4. "ordering information" on page 7. updated figure 3, ?part number convention,? on page 7.
si532 preliminary rev. 0.3 9 n otes :
si532 10 preliminary rev. 0.3 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email:vcxoinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.
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